Free delivery for orders over 69.99 euro.

Check order status

Become part of a community of book lovers from all over the world and get access to a whole bunch of benefits. Create an account for free

Free delivery for purchases over 69.99 €

DPD courier 5.99 € Bpost point 7.99 € Bpost 7.49 € DPD point 3.49 € GLS courier 4.99 €

Contact

How to shop

Help

My account

▸ Empty :-(

Free delivery for orders over 69.99 euro.

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Name: Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
Brand: Springer International Publishing AG
SKU: 02076816
Price: 100.68 EUR
Availability: InStock
Author: Brandon Noia
ISBN: 9783319023779

Brandon Noia

Krishnendu Chakrabarty

Language

English

Book Hardback

Libristo code: 02076816

Publishers Springer International Publishing AG, November 2013

This book describes innovative techniques to address the testing needs of 3D stacked integrated circ... Full description

Libristo code: 02076816

244 b

100.68 €

In stock at our supplier Shipping in 10-13 days

Up to 30 days for returns

Customers also purchased

Blatter Fur Technikgeschichte Dr. Phil. Josef Nagler

Paperback

53.57 €

Benjamin Blümchen, Gute-Nacht-Geschichten - Badespaß im Zoo, 1 Audio-CD Benjamin Blümchen/Gute-Nacht-Geschichten

Audio CD

10.91 €

Qualitätsgerechte Auslegung flexibler Produktionssysteme mit Hilfe von Simulation Egbert Englert

Paperback

53.06 €

Multimedia-PCs für telekooperatives Arbeiten Michael Jäger

Paperback

53.06 €

Der Boden ALS Oberste Schicht Der Erdoberfl che E. Blanck

Paperback

53.06 €

Az ego az ellenség - Bővített kiadás Ryan Holiday

Hardback

12.22 €

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.