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Layout Optimization in VLSI Design
Language
English
English
Book
Paperback
The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout op...
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Libristo code: 01423530
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The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as interconnect delay, noise, crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout optimization problems emerging with the advent of very deep submicron technologies in semiconductor processing. §Audience: A reference work for graduate students, senior undergraduates, and researchers.
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About the book
Full name
Layout Optimization in VLSI Design
Author
ing Lu, ing-Zhu Du, S. Sapatnekar
Language
English
English
Binding
Book - Paperback
Date of issue
2010
Number of pages
288
EAN
9781441952066
ISBN
1441952063
Libristo code
01423530
Publishers
Springer, Berlin
Weight
481
Dimensions
160 x 240 x 16
Categories
Technology, Engineering, Agriculture
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Electronics & communications engineering
>
Electronics engineering
>
Electronics: circuits & components
Computing & Information Technology
>
Graphical & digital media applications
>
Computer-aided design (CAD)
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